sidhantp1906

4-Request-First-Come-First-Serve-Arbiter

4 request first come first serve arbiter design using verilog HDL

Adcanced_Digital_Logic_Design-01fe19bec187

Lab projects using Verilog HDL

AMBA4-APB

Advanced Pheripheral Bus design using verilog HDL

binary-to-csd

verilog code to covert binary number into canonical signed digit(csd)

csd-multiplier-using-booth-technique

csd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.

IEEE-latex-report

IEEE-latex-report for 32-bit CSD multiplier

Resume

Contains my resume

RTC-Real-Time-Clock-

Design of real time clock(RTC) using Verilog HDL

TicTacToe

TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board

Vending-machine

Soda & Water Vending Machine with Return & Refund functionality designed using Verilog HDL

sidhantp1906/4-Request-First-Come-First-Serve-Arbiter

4 request first come first serve arbiter design using verilog HDL

sidhantp1906/RTC-Real-Time-Clock-

Design of real time clock(RTC) using Verilog HDL

sidhantp1906/Adcanced_Digital_Logic_Design-01fe19bec187

Lab projects using Verilog HDL

sidhantp1906/binary-to-csd

verilog code to covert binary number into canonical signed digit(csd)

sidhantp1906/TicTacToe

TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board

sidhantp1906/AMBA4-APB

Advanced Pheripheral Bus design using verilog HDL

sidhantp1906/csd-multiplier-using-booth-technique

csd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.

sidhantp1906/IEEE-latex-report

IEEE-latex-report for 32-bit CSD multiplier

sidhantp1906/Resume

Contains my resume

sidhantp1906/Vending-machine

Soda & Water Vending Machine with Return & Refund functionality designed using Verilog HDL

sidhantp1906/4-bit-first-divider

4 bit divider design using first divider algorithm

sidhantp1906/8-bit-first_multiplier

verilog design of first multiplier design and architecture

sidhantp1906/Analog-Hackathon-Data-Encryption-

2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology

sidhantp1906/analog-to-digital-clock-generator

Here i designed a converter circuit which converts analog sine signal to digital clock signal.This is my personal work which suddenly came into my mind so i designed.I used half wave rectifier circuit with filter to get +ve half of sine wave and then used comparator to convert that into square wave which is digital clock output.

sidhantp1906/Automation-with-python

basic projects using python

sidhantp1906/dsp-open-ended

sidhantp1906/eSIM-Marathon

designed a simple D-flipflop from JK-flipflop using eSIM and SKY130nm pdk

sidhantp1906/FCFS_Arbiter_Design_And_Verification

Design and verification of first come first serve arbiter

sidhantp1906/googlecolab_python

learning python

sidhantp1906/googlekickstart2020

practicing 2020 google kickstart questions using python

sidhantp1906/guess-game-using-python

i have designed a beautiful guess game using python. Lerning python part3

sidhantp1906/lottery-game

lottery game using python

sidhantp1906/OpenCV

learning opencv basics

sidhantp1906/PulseWidthModulation

PWM module using verilig HDL in XILINX ISE

sidhantp1906/RISCV-RV32IM

sidhantp1906/RV32I

I worked personally on designing rv32i processor for some of the instructions like add,addi,sub,etc..

sidhantp1906/sidhantp1906

Config files for my GitHub profile.

sidhantp1906/social-distance-maintainer

social distance maintainer using arduino uno R3

sidhantp1906/Starting-with-ML-

basic problem statements and solution of machine learning

sidhantp1906/UART

UART implementation using Verilog HDL