UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches.

Overview, Readability, Maintainability, Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 as a to handle exactly these aspects.

UVVM consists currently of the following elements

Utility Library
VVC (VHDL Verification Component) Framework - Including Utility Library
BFMs (Bus Functional Models) to be used with any part of UVVM (See below for currently supported interfaces from Bitvis)
VVCs to be used with UVVM VVC Framework and may be combined with BFMs (see overview below) more to come...

For what do I need this VVC Framework?

UVVM is a verification component system that allows the implementation of a very structured testbench architecture to handle medium complexity verification challenges and upwards. A key benefit of this system is the very simple software-like VHDL test sequencer that may control your complete testbench architecture with any number of verification components. This takes overview, readability and maintainability to a new level. As an example a simple command like uart_expect(UART_VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_message) will automatically tell the respective VVC (for UART or AXI-Lite) to execute the uart_receive() or axilite_write() BFM respectively.

What are the main benefits of using this system?

The really great benefit here is the unique overview, readability, maintainability, extensibility and reuse you get from having the best testbench architecture possible - much in the same way as a good architecure is also critical for any complex design. Another major benefit here is that any number of commands may be issued at the same time from the test sequencer - thus allowing full control of when an access is to be performed, and the commands are understandable "even" for a software developer ;-) The commands may be queued, skewed, delayed, synchronised, etc - and a super-set for applying constrained random or other sequences of data may of of course also be applied. This yields an excellent control over your testbench and VVCs.

For debugging you can select logging of a command when it is issued from the sequencer, when it is received by the VVC, when it is initiated by the VVC and/or when it has been executed towards the DUT. This allows full overview of all actions in your complete testbench.

You may of course combine UVVM with any other legacy or 3rd party testbenches or verification models. This post on LinkedIn will give you some more info on why you should use this library.

Main Features

Very usefull support for checking values, ranges, time aspects, and for waiting for events inside a given window
An extremely low user threshold for the basic functionality - like logging, alert handling and checkers
A very structured testbench architecture that allows LEGO-like testbench/harness implementation
A very structured VHDL Verification Component (VVC) architecture that allows simultaneous activitity (stimuli and checking) on multiple interfaces in a very easily understandable manner
An easily understandable command syntax to control a complete testbench with multiple VVCs
The structure and overview is easily kept even for a testbench with a large number of VVCs
A VVC architecture that is almost exactly the same from one VVC to another - sometimes with only the BFM calls as the differentiator, thus allowing an extremely efficient reuse from one VVC to another
A VVC architecture that easily allows multiple threads for e.g. simultaneous Avalon Command and Response
A VVC architecture that allows simple encapsulation for ALL verification functionality for any given interface or protocol
Allows VVCs to be included anywhere in the test harness - or even inside the Design it self
A logging and alert system that supports full verbosity control of functionality and hierarchy
A logging system that lets you easily see how your commands propagate from your central test sequencer to your VVCs - through the execution queue - until it is executed and completed towards the DUT
Allows OSVVM randomisation and functional coverage to be included in the central test sequencer - or even better - inside the VVCs in the local sequencers for better control and encapsulation
Simple integration with regression test tools like Jenkins
Quick references are available for UVVM Utility Library, VVC System and all the BFMs/VVCs

Available VVCs and BFMs

These VVCs and BFMs could be used inside a typical UVVM testbench, but they could also be used stand-alone - e.g. as a BFM or VVC to handle just the AXI4-Lite interface with everything else being your proprietary testbench and methodology.

AXI4-Lite
AXI-Stream
Avalon MM
SBI (Simple Bus Interface - A single cycle simple parallel bus interface)
UART
SPI
I2C
More are coming

Prerequisites

UVVM is tool and library independent, but must be compiled with VHDL 2008. UVVM has been tested with the following simulators:

Modelsim version 10.3d
Riviera-PRO version: 2015.10.85

Python is required if you want to execute the VVC generation scripts

Introduction to VVC Framework - including manuals

All documents including powerpoint presentations are available in the doc-directory of VVC_Framework on GitHub. This is just a fast access link to some interesting info:

'The critically missing VHDL testbench feature - Finally a structured approach' - A brief introduction
'VVC Framework Manual' - The user manual

License

The MIT License (MIT)

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

UVVM Maintainers

Bitvis (Norway) has released UVVM as open source and we are committed to develop this system further. We do however appreciate contributions and suggestions from users.

sigasi/UVVM_All