Sigasi

Pinned Repositories

com.sigasi.ultraedit.bindings
UltraEdit key bindings scheme for Eclipse
0 4 01
sigasi_demos
Language:SystemVerilog9 10 03
sigasi_documentation_examples
This repository contains examples of documentation that has been generated using Sigasi Studio.
Language:HTML1 3 00
sigasi_insights
Language:HTML3 9 39
sigasi_online_demo
Demo project
Language:VHDL2 6 00
sigasi_training
Training material for Sigasi software
Language:VHDL1 11 00
SigasiProjectCreator
Python scripts that help generating custom Sigasi Project and Libary configuration files
Language:Python16 11 2311
vhdl2008-tester
Language:VHDL0 3 00
www.systemverilogeditor.com
Urubu website content for www.systemverilogeditor.com
Language:HTML00
XilinxTclStore
Xilinx Tcl Store
Language:Tcl0 4 00

Sigasi's Repositories

sigasi/SigasiProjectCreator
Python scripts that help generating custom Sigasi Project and Libary configuration files
Language:Python16 11 2311
sigasi/sigasi_demos
Language:SystemVerilog9 10 03
sigasi/sigasi_insights
Language:HTML3 9 39
sigasi/sigasi_online_demo
Demo project
Language:VHDL2 6 00
sigasi/sigasi_documentation_examples
This repository contains examples of documentation that has been generated using Sigasi Studio.
Language:HTML1 3 00
sigasi/sigasi_training
Training material for Sigasi software
Language:VHDL1 11 00
sigasi/com.sigasi.ultraedit.bindings
UltraEdit key bindings scheme for Eclipse
0 4 01
sigasi/Sigasi_CLI_in_CI_demo
A demonstration of how the Sigasi CLI can be used in a CI/CD pipeline
Language:SystemVerilog0 6 10
sigasi/vhdl2008-tester
Language:VHDL0 3 00
sigasi/www.systemverilogeditor.com
Urubu website content for www.systemverilogeditor.com
Language:HTML00
sigasi/XilinxTclStore
Xilinx Tcl Store
Language:Tcl0 4 00
sigasi/eclipse_custom_code_checker
Language:Python3 0
sigasi/EMF-Statistics-View
Eclipse support for viewing the statistics of a EMF model associated with the active editor.
3 0
sigasi/markermanager_doc
Language:HTML1
sigasi/mips_r2000
Language:VHDL4 0
sigasi/opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilog
sigasi/sigasi-csv-build
Language:Python2 0
sigasi/sigasi-tmlanguage
provide VHDL and SV syntax highlighting
8 0
sigasi/sigasi_demo
Language:VHDL9 0
sigasi/sigasi_premium_tutorial
Language:VHDL
sigasi/sigasi_theme
Hugo theme used for Sigasi websites
Language:JavaScript
sigasi/uvm-in-vunit-tutorial-simple-adder
A demonstration of how to run UVM tests in VUnit
Language:SystemVerilog1 0
sigasi/UVVM_All
Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
Language:VHDL4 0
sigasi/veresta-doc
Generate Sigasi project documentation in CI
Language:SystemVerilog1 0