sinanmert1

sinanmert1's Stars

• saiedhk/WhirlpoolHashEngine

  WHIRLPOOL Hash Engine in Verilog

  Language:Verilog1

• secworks/sha1

  Verilog implementation of the SHA-1 cryptgraphic hash function

  Language:Verilog5218

• freecores/nfhc

  Nugroho Free Hash Cores

  Language:VHDL1

• adspirop/SHA-1-VHDL

  Implementation of SHA-1 core in VHDL for FPGA Using Pipeline

  Language:VHDL41

• lostpfg/SHA-256-HDL

  An implementation of original SHA-256 hash function in (RTL) VHDL

  Language:VHDL82

• ikwzm/SECURE_HASH

  SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).

  Language:VHDL115

• aletempiac/DES-cracker

  DES cracking machine on FPGA

  Language:VHDL198

• pedrorivera/SiaFpgaMiner

  VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

  Language:VHDL6233

• maddineninikhil/Blake2b-512

  This is a sample Python code for Blake2b-512 implementation

  Language:Jupyter Notebook3

• aaruel/Serpent-Implementation

  C and VHDL Full Implementation of AES candidate cipher

  Language:VHDL41

• PravallikaBoddupalli/DES

  Data Encryption Standard Project in Python

  Language:Python1

• ymei/K71GbE

  KC705 topmodule with gigabit ethernet (TCP)

  Language:VHDL34

• hpcn-uam/efficient_checksum-offload-engine

  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream interface.

  Language:VHDL166

• neicullyn/tcp_stack_rebuild

  Language:VHDL1

• neicullyn/TCP_full_stack

  Language:VHDL2

• eminfedar/fedar-f1-rv64im

  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

  Language:Verilog19119

• kaanberke/youtube_courses

  Language:Jupyter Notebook6728