sohunpatel

sohunpatel's Stars

• mikeroyal/Neuromorphic-Computing-Guide

  Learn about the Neumorphic engineering process of creating large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures.

  Language:Python31946

• jzarnett/ece459

  ECE 459: Programming for Performance

  Language:TeX436136

• renerocksai/rrisc

  Creating a small microprocessor: VHDL implementation of my RRISC CPU

  Language:VHDL8

• rafamedina97/FPGA_SNN_STDP

  FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks

  Language:VHDL337

• SFU-HiAccel/SyncNN

  [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.

  Language:C++505

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.6k408

• Shikhargupta/Spiking-Neural-Network

  Pure python implementation of SNN

  Language:Python1k284

• tymonx/logic

  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

  Language:SystemVerilog26658

• dannyneil/edbn

  Event-based deep belief network offline training algorithm

  Language:Matlab2114

• sfox14/pynq-ekf

  A multi-board Extended Kalman Filter (EKF)

  Language:Tcl2811

• oshears/fpga_snn_models

  A repository FPGA-friendly SNN models

  Language:Python275

• jasha64/SNN-FPGA

  Spiking Neural Network RTL Implementation

  Language:SystemVerilog419

• hillhao/PYNQ-project

  PYNQ, Neural network Language model, Overlay

  Language:Jupyter Notebook10035

• kelu124/echomods

  Open source ultrasound processing modules and building blocks

  Language:Jupyter Notebook33198

• Domipheus/RPU

  Basic RISC-V CPU implementation in VHDL.

  Language:VHDL15816

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.3k153

• hamsternz/Rudi-RV32I

  A rudimental RISCV CPU supporting RV32I instructions, in VHDL

  Language:VHDL11316

• skordal/potato

  A simple RISC-V processor for use in FPGA designs.

  Language:VHDL25640

• chipsalliance/VeeRwolf

  FuseSoC-based SoC for VeeR EH1 and EL2

  Language:Verilog27764

• n0tsteve/Genshin-Map-Helper

  Best genshin software for map research, full legit helper without analogues.

  11311

• lipido/todoswing

  A simple TO-DO list in Java Swing

  Language:Java58

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k281

• cyrus-and/gdb-dashboard

  Modular visual interface for GDB in Python

  Language:Python10.9k765

• ultraembedded/minispartan6-audio

  miniSpartan6+ (Spartan6) FPGA based MP3 Player

  Language:Verilog257

• zephyrproject-rtos/example-application

  Example out-of-tree application that is also a module

  Language:C213125

• zephyrproject-rtos/zephyr

  Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

  Language:C10.4k6.4k

• libopencm3/libopencm3

  Open source ARM Cortex-M microcontroller library

  Language:C3k1k

• Marus/cortex-debug

  Visual Studio Code extension for enhancing debug capabilities for Cortex-M Microcontrollers

  Language:TypeScript984238