/VLSI-Logical-Effort-

Primary LanguageGnuplot

VLSI-Logical-Effort-

Using ngspice, designing a minimum sized CMOS inverter such that the rise time and fall time are equal for some load capacitance. Evaluating the inverter delay for different fanouts(DUT with 1, 2, 3, . . . 8 inverters) and thus understanding the concept of logical effort.

Architecture

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