srimanthtenneti
SoC Physical Design Intern @ Apple | EE Grad Student @ University of Cincinnati | Ex - IP Engineering Intern @ Open-Silicon | Ex- Deep Learning Intern @ NVIDIA
University of CincinnatiSunnyvale, California
Pinned Repositories
Autoencoders
For image and audio compression and decompression
Convolution-Layer-Visualizer
Deep-Learning-NanoDegree
FeFET-Programming-Network-
Pulse varying circuits for FeFET programming
Hell_Fire_SoC_Demo
Language_Transformer
This is the implementation of a decoder only transformer on a small dataset. The model contains about 10.8M parameters.
RISC-CPU-Components
Components like ALU, Memory, Control Unit, etc to build a RISC Based CPU.
Simple-Perceptron
This project aims to build a simple perceptron model for embedded systems. This repo is the initial version of the model.
SOC-Design-ARM-M0
This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
Systolic_Arrays
This repo contains an implementation of a 2x2 Systolic Array using Verilog HDL. The testbench is also included in the design file.
srimanthtenneti's Repositories
srimanthtenneti/Hell_Fire_SoC_Demo
srimanthtenneti/SOC-Design-ARM-M0
This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
srimanthtenneti/Autoencoders
For image and audio compression and decompression
srimanthtenneti/RISC-CPU-Components
Components like ALU, Memory, Control Unit, etc to build a RISC Based CPU.
srimanthtenneti/Systolic_Arrays
This repo contains an implementation of a 2x2 Systolic Array using Verilog HDL. The testbench is also included in the design file.
srimanthtenneti/Convolution-Layer-Visualizer
srimanthtenneti/Deep-Learning-NanoDegree
srimanthtenneti/FeFET-Programming-Network-
Pulse varying circuits for FeFET programming
srimanthtenneti/Language_Transformer
This is the implementation of a decoder only transformer on a small dataset. The model contains about 10.8M parameters.
srimanthtenneti/UART_Implementation_FPGA
Design and Implementation of a UART Transreciever.
srimanthtenneti/Cardiac-Abnormality-Detection
srimanthtenneti/Byte_Pair_Encoding
This is a tokenization scheme typically used in modern day LLMs. The following implementation builds this scheme from scratch using basic python libraries.
srimanthtenneti/D12-MiniProject-Demo
srimanthtenneti/Datasets
srimanthtenneti/DCGANs
Deep Convolutional Generative Adversarial Networks
srimanthtenneti/Deep_Learning_Workshop_Sept2021
srimanthtenneti/Dolly_Web_App
srimanthtenneti/FashionMNIST-CNN
srimanthtenneti/Images
srimanthtenneti/IOT_Demo
Embedded interfacing , Data Streaming(Video) , Cloud Connect ,Machine Learning and Convolutional Neural Networks
srimanthtenneti/MakeUC_Submission
The implemented solution tries to implement a Vaccine distribution system that considers people's sentiments and creates a geospatial cluster map of opinions that the governments could use to efficiently distribute the vaccines in regions where people would like to have them.
srimanthtenneti/MIPS_32_BIT_CPU
srimanthtenneti/ML-Workshops
srimanthtenneti/Playing_With_Gaussians
1D Kalman Filter Implementation
srimanthtenneti/PSOC6-Design-Contest
This repository describes my PSOC6 design contest project where I built a cloud based patient monitoring interface using PSOC6 as a core BLE based data filter and aggrigator.
srimanthtenneti/Secure-vehicle-tracking
srimanthtenneti/Tensorflow101
This repository is for the DSC CVR Tensorflow101 session where we would look at implementing Artificial Neural Networks & Convolutional Neural Networks using Tensorflow. Also, we would be implementing some machine learning models too.
srimanthtenneti/Verilog-Implementations
This Repository contains synthesizable implementations of various modules in verilog.
srimanthtenneti/vgg16
srimanthtenneti/X1CPU
Simple Accumulator based Von Neumann CPU