srinivasg137

I am an FPGA/ASIC RTL design engineer. I have 8+ years of experience in micro-architecture, RTL design.

Pinned Repositories

clock-domain-crossing
This repository contains various clock domain crossing verilog modules
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l2_switch
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test
my test repo - first one
Language:Verilog00

srinivasg137's Repositories

srinivasg137/test
my test repo - first one
Language:Verilog
srinivasg137/clock-domain-crossing
This repository contains various clock domain crossing verilog modules
srinivasg137/l2_switch