/RISCV-RV32I-CORE

Primary LanguageC++

RISCV-RV32I-CORE

This repository contains RISCV (RV32I) Single Cycle Processor RTL design in SystemVerilog and Testbench in C++.

Tools:

-Verilator

-Fusesoc

Tools Version:

-Verilator : 4.212

-Fusesoc : 1.12.0

Circuit Diagram:

Processor

Assembly Code Link:

-Assembly Codes: Testing on RISC-V Core

GTKWaves Demonstration:

gtkwave1 gtkwave2 gtkwave3

References:

-Verilator Manual

-Fusesoc Manual