Pinned Repositories
emmc_test
Formal_Verification
Coverage Closure and Bug Hunt Project
gmii_mirror_xgmii
mipi_mphy
Specification for mipi-M-PHY
NAND-Flash-Memory-Controller-verification
Python-100-Days
Python - 100天从新手到大师
SDRAM-Controller
EDEC STANDARD Double Data Rate (DDR) SDRAM Specification
SYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
system-verilog-patterns
SystemVerilog Design Patterns
zipcpu
A small, light weight, RISC CPU soft core
tanbour's Repositories
tanbour/Formal_Verification
Coverage Closure and Bug Hunt Project
tanbour/gmii_mirror_xgmii
tanbour/zipcpu
A small, light weight, RISC CPU soft core
tanbour/antikernel
The Antikernel operating system project
tanbour/antikernel-ipcores
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
tanbour/aq_mipi_csi2rx_ultrascaleplus
tanbour/chisel3
Chisel 3
tanbour/cocotb
Coroutine Co-simulation Test Bench
tanbour/cores
Various HDL (Verilog) IP Cores
tanbour/Design-Verification
Course content for the University of Bristol Design Verification course.
tanbour/Exploring-Zynq-MPSoC-CN
Exploring Zynq ® MPSoC Chinese
tanbour/firrtl
Flexible Intermediate Representation for RTL
tanbour/FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
tanbour/fpga_pio
An attempt to recreate the RP2040 PIO in an FPGA
tanbour/Functional-Safety-Notes
基于Xilinx平台的功能安全笔记
tanbour/gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
tanbour/gen_apb_file
tanbour/QSPI_FOR_SOC
QSPI for SoC
tanbour/qspiflash
A set of Wishbone Controlled SPI Flash Controllers
tanbour/rggen-verilog
Verilog writer plugin for RgGen
tanbour/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
tanbour/sim_core
tanbour/sim_prj
tanbour/swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
tanbour/swerv_sim
simulation env for swerv_th1, which is base on vcs & verdi
tanbour/tsn
tanbour/UART_VLC_Transmission
UART (9600/115200) to VLC (RS code/Manchester code/8x Sampling Syncronization)
tanbour/Udacity-Functional-Safety-Notes
tanbour/UVM-related-topics
tanbour/wujian100_open
IC design and development should be faster，simpler and more reliable