taneroksuz/wolv-z1

Wolv Z1 is a RISC-V CPU core

Wolv Z1 CPU core

Wolv Z1 CPU core supports currently only riscv32-imcb instruction set architecture and is implemented with 3-stage pipeline and Neumann bus architecture.

Dhrystone Benchmark

Cycles	Dhrystone/s/MHz	DMIPS/s/MHz	Iteration
336	2975	1.69	1000

Coremark Benchmark

Cycles	Iteration/s/MHz	Iteration
339742	2.94	10

Documentation will be expanded in the future.