Issues
- 0
Help with design low-level HDL language
#30 opened - 2
Undeclared `_FSM` reg breaks `sequence`
#29 opened - 0
- 0
What is the testing story?
#27 opened - 0
Add FSM variable naming.
#26 opened - 0
Add fixed width literals.
#25 opened - 1
Keywords "def" and "def mut"
#24 opened - 0
Add typeck for unassigned vars.
#23 opened - 0
- 1
- 0
Video generation is currently broken
#20 opened - 1
Fix "make clean" issue
#19 opened - 1
Remove always blocks
#18 opened - 0
Add primitive typeck for def and def mut
#17 opened - 1
- 1
- 0
Consider full_case and parallel_case
#14 opened - 0
Support multiple clk sources
#13 opened - 1
- 0
- 1
Error for unknown variable names
#10 opened - 1
- 1
- 1
uint{..16} and int{..16} testing
#7 opened - 0
How "fsm" should work
#6 opened - 0
How "reset" should work
#5 opened - 1
Entity definitions
#4 opened - 0
Macros/functions/templates
#3 opened - 1
- 0
Different FSM types
#1 opened