Pinned Repositories
blif2verilog
Simple blif to verilog converter in C++
chipwhisperer
ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
Chipwhisperer-AES128-CW308-S6LX9-target
Digital_Path_Timing_Monitor
Fortuna-CSPRNG
Hardware implementation of the Fortuna PRNG algorithm
iacrtrans
LaTeX class for the IACR Transactions on Symmetric Cryptology
my-dotfiles
My tmux and neovim config
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OPTEE-OS-Build
OPTEE OS build makefiles
Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
tebina's Repositories
tebina/blif2verilog
Simple blif to verilog converter in C++
tebina/chipwhisperer
ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
tebina/Chipwhisperer-AES128-CW308-S6LX9-target
tebina/Digital_Path_Timing_Monitor
tebina/Fortuna-CSPRNG
Hardware implementation of the Fortuna PRNG algorithm
tebina/iacrtrans
LaTeX class for the IACR Transactions on Symmetric Cryptology
tebina/my-dotfiles
My tmux and neovim config
tebina/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
tebina/OPTEE-OS-Build
OPTEE OS build makefiles
tebina/Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
tebina/Ray-Spect
A tool to insert parametric modifications into a specter netlist
tebina/Simple-UART-SystemVerilog
tebina/tebina.github.io
tebina/WavePropagator
tebina/wb2axip
Bus bridges and other odds and ends