thbuehler

thbuehler's Stars

• pulp-platform/common_cells

  Common SystemVerilog components

  Language:SystemVerilog541146

• sudhamshu091/32-Verilog-Mini-Projects

  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

  Language:Verilog602117

• taichi-ishitani/tnoc

  Network on Chip Implementation written in SytemVerilog

  Language:SystemVerilog16144

• jcorbisiero/NOC

  SystemVerilog Network On Chip for Computer Hardware Design Class

  Language:Tcl67

• karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2

  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator

  Language:SystemVerilog13429

• ljhsiun2/EllipticCurves_SystemVerilog

  Elgamal's over Elliptic Curves

  Language:SystemVerilog194

• nelsoncsc/sv_image

  Reusable image processing modules in SystemVerilog

  Language:SystemVerilog338

• agalimberti/NoCRouter

  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

  Language:SystemVerilog11837

• zhouchuanrui/Cryptography-in-Systemverilog

  A collection of cryptographic algorthms implemented in SystemVerilog

  Language:SystemVerilog197

• luuvish/system-verilog-patterns

  SystemVerilog Design Patterns

  Language:SystemVerilog267

• cjdrake/AES

  Advanced Encryption Standard (AES) SystemVerilog Core

  Language:SystemVerilog3414

• bespoke-silicon-group/basejump_stl

  BaseJump STL: A Standard Template Library for SystemVerilog

  Language:SystemVerilog53699

• unixb0y/SystemVerilogSHA256

  SHA256 in (System-) Verilog / Open Source FPGA Miner

  Language:SystemVerilog7726

• zachjs/sv2v

  SystemVerilog to Verilog conversion

  Language:Haskell57455

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL756267

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.7k384

• airin711/Verilog-caches

  Various caches written in Verilog-HDL

  Language:Verilog11441

• eirikpre/VSCode-SystemVerilog

  SystemVerilog support in VS Code

  Language:TypeScript13150

• alexforencich/verilog-lfsr

  Fully parametrizable combinatorial parallel LFSR/CRC module

  Language:Python14055

• chipsalliance/f4pga-examples

  Example designs showing different ways to use F4PGA toolchains.

  Language:Verilog27078

• thomasrussellmurphy/istyle-verilog-formatter

  Open source implementation of a Verilog formatter

  Language:C++17645

• TerosTechnology/vscode-terosHDL

  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  Language:VHDL57947

• avakar/usbcorev

  A full-speed device-side USB peripheral core written in Verilog.

  Language:Verilog21840

• dalance/svlint

  SystemVerilog linter

  Language:Rust32334

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  50048

• chipsalliance/sv-tests

  Test suite designed to check compliance with the SystemVerilog standard.

  Language:SystemVerilog30475

• veripool/verilog-mode

  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

  Language:SystemVerilog26491

• secworks/aes

  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

  Language:Verilog340126

• MikePopoloski/slang

  SystemVerilog compiler and language services

  Language:C++646142

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k216