thommythomaso

Pinned Repositories

axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language:SystemVerilog1.1k 39 119256
cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Language:Verilog184 14 1639
common_cells
Common SystemVerilog components
Language:SystemVerilog499 19 55140
hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
Language:SystemVerilog93 10 024
iDMA
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Language:SystemVerilog87 7 926
register_interface
Generic Register Interface (contains various adapters)
Language:SystemVerilog95 6 424
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
Language:SystemVerilog218 20 7372
snitch
⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
Language:SystemVerilog218 9 5052
snitch_cluster
An energy-efficient RISC-V floating-point compute cluster.
Language:C49 10 5248
tt03-tbenz
TBD
Language:Tcl0 0 00