tmeissner
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.
Dresden, Germany
tmeissner's Stars
google/comprehensive-rust
This is the Rust course used by the Android team at Google. It provides you the material to quickly teach Rust.
paperless-ngx/paperless-ngx
A community-supported supercharged version of paperless: scan, index and archive all your physical documents
adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
veorq/cryptocoding
Guidelines for low-level cryptography software
tillitis/tillitis-key1
Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑
rancilio-pid/clevercoffee
Do-It-Yourself PID für Espressomaschinen
chipsalliance/synlig
SystemVerilog support for Yosys
raysalemi/Python4RTLVerification
Fraunhofer-IMS/airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
aman-goel/avr
Reads a state transition system and performs property checking
Forty-Bot/ethernet
WIP 100BASE-TX PHY
stnolting/neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
gsmecher/pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator
jgrahamc/gmsl
GNU Make Standard Library
colognechip/gatemate_ila
The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the FPGA can be monitored in a waveform.
gabriele-galeotti/SweetAda
Ada-language framework
mbgh/aes128-hdl
A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
pgroupATusc/fasthash
Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
reactive-systems/MCHyper
A hardware model checker for hyperproperties
tmeissner/gatemate_experiments
Experiments with Cologne Chip's GateMate FPGA architecture
Chair-for-Security-Engineering/AES_masked_BRAM
Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
fm4dd/gatemate-riscv
RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
INRS-ECCoLe/DSCAM
Directly Synthesized Content-Addressable Memory (DSCAM) is an innovative method to implement very large CAMs on FPGAs. DSCAM offers guaranteed low-latency and high throughput lookups with an affordable resource utilization compared to related works.
miree/gvi
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
stnolting/neorv32-formal
Formal verification (experiments) targeting the NEORV32 RISC-V processor.
teknoman117/PCIEX1-SMA
Low-cost PCIe x1 to SMA adapter
OSVVM/CoSim
OSVVM submodule for Co-simulation features
emaicas/dvstuff
lauterbach-mirror/jswitch
Mirror of Lauterbach's JSwitch VHDL IP
motius/neorv32
:desktop_computer: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.