cpu-architecture
There are 41 repositories under cpu-architecture topic.
arm-university/Introduction-to-Computer-Architecture-Education-Kit
Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors
arm-university/Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
A textbook on understanding system on chip design
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
MaorAssayag/Architecture-of-CPU-projects
VHDL , ModelSIM, Quartus, FPGA, Image Processing
RossComputerGuy/SherwoodArch
The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.
laskarelias/upatras-riscv
Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras
AkhilRai28/ALUBuilder
A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.
JimCownie/CpuFun
Code snippets for the CpuFun blog
MIPT-ILab/MDSP
[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor
uros-bojanic/8-bit-computer
[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.
amari-calipso/custom-emulated-computer
A 16-bit computer architecture i made, emulated in opal
codehasan/MyArch
📱 An app to view all supported ABI of the running device
eomielan/16-bit-RISC-machine
16-bit CPU architecture implementation and verification using SystemVerilog
erwanregy/Cache-Simulation
CPU Cache Simulation using gem5
Kammann123/ev21g1
General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board
MartinBrugnara/archetypum
Tomasulo algorithm visualizer
schemil053/ScheCPUEmulator
This is a simple CPU emulator with custom architecture
cedrickchee/nand2tetris
Solutions for http://www.nand2tetris.org/
erwanregy/NoC-Simulation
Network-on-Chip Simulation using Noxim
ewpratten/Dirobium
The virtual CPU (and emulator) built for hobbyists
Haaris-RTL/8-bit-CPU
RTL code of an 8-bit CPU designed in Verilog.
MEESAM749/RISC-V-PipelinedProcessor
RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE
MEESAM749/Single-Cycle-Non-Pipelined-MIPS-32-Processor
This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.
onegentig/VUT-FIT-INP2022-projekt1
První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023
Sayemum/CS261-Y86-CPU-Simulator
My semester-long project for CS261 - Computer Systems at James Madison University where I constructed a cpu simulator using a smaller version of x86 called y86.
SexySparrow/RISC_V
RISC-V CPU arhitecture
arinaivanova/logisim-cpu
WIP: CPU implemented in LogiSim from NAND gates.
DebasishPanda529/EE309_IITB-RISC
Github repo containing all the VHDL files for the EE309 course project involving designing a 16-bit, 6-staged pipelined processor based on the RISC ISA.
mohdfahad12328/scpu
a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works
simon-gardier/cpu-design
📟 32 bits CPU design
ThiagoDSMarcelino/cpu-architecture
16-bit CPU with specific Assembler for Assembly codes capable of controlling a 32x32 led screen
Hridxyz/Microprocessor-Assembly-Language
A repository of my assembly language learning journey, featuring programs that illustrate the core principles of microprocessor operations and low-level coding.
Mariuspersen/cisc64
Idea for a new type of architecture
p4ulor/Eletronics-n-Computer-Design
🔌 Electronics, logic dates, digital circuits & CPU design/architecture. ISEL college subjects: LSD, AC, LIC
ParkerTenBroeck/MyCPU_16bit
A 16 bit SAP-1 CPU that I designed in grade 10 designed in logisim