DebasishPanda529/EE309_IITB-RISC

Github repo containing all the VHDL files for the EE309 course project involving designing a 16-bit, 6-staged pipelined processor based on the RISC ISA.

IITB-RISC

Course Instructor :- Prof. Virendra Singh

Team members :-

• Debasish Panda [21D070021]
• Bhakti Matsyapal [210070021]
• Ayan Das [210070016]
• Anuja Sathe [210070010]

IITB-RISC is a 16-bit elementary computer developed for teaching that is based on the Little Computer Architecture. It has 8 general-purpose registers (R0 to R7). It follows the standard 6-stage pipeline, namely- Instruction Fetch (IF), Instruction Decode (ID), Register Read (RR), Execute (EX), Memory Access (MA), and Write Back (WB). Ideally, the architecture should be optimized for performance, i.e., it should also include hazard-mitigation techniques, such as data-forwarding and branch prediction.

N.B. : The reader is advised to exercise caution while using the code as a reference. Although the fundamental idea behind the code is more or less correct, we were unable to verify the correctness of the code for various instructions through testing and verification. Constructive suggestions regarding any change in the code are most welcome, and can be mailed here.