digital-logic-design
There are 154 repositories under digital-logic-design topic.
logisim-evolution/logisim-evolution
Digital logic design tool and simulator
yupferris/kaze
An HDL embedded in Rust.
Akashtailor-exe/30-days-of-verilog
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
fuad1502/oombak
Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
madhurimarawat/Semester-Notes
This repository includes academic notes, study materials, and resources from B.Tech (Hons) in CSE, specializing in Artificial Intelligence and Data Science. It features question papers, proprietary study guides, and resources to support learning in these fields.
raycar5/logicsim
Composable digital logic simulation in Rust!
MuxammilSidd/FAST-KHI-Semester-2
FAST NUCES Karachi - BSCS Second Semester Repository | Access notes, assignments, past papers, & more. For queries or suggestions, contact k232001@nu.edu.pk.
shrine-maiden-heavy-industries/torii-hdl
A Python-based HDL and framework for silicon-based witchcraft
Multimedia-Processing/Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
AryCra07/TougHardware
BUPT 数字逻辑与数字系统课程设计项目
Amey-Thakur/DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
SM2A/University_Projects
🎓💻All of my projects at University of Tehran
harismuneer/Car-Parking-Controller
🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"
rohankalbag/vlsi-design
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
azizi-zahra/simple-vending-machine
DLD Project - A simple vending machine simulation with Verilog (Spring 2024)
ChaminduS/Building-a-RISC-V-CPU-Core
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
hasnainroopawalla/circuit-sim
Digital logic gate simulator using React, TypeScript and p5.js
ShashankVM/generic_systemverilog_designs_library
A library of useful, fully parameterized RTL designs implemented in SystemVerilog.
skamal16/Mobile-Trainer-Board
My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.
Bh4r4t/32-bit-Divider
32-bit Divider circuit implemented using Verilog
danielkim802/PyLogic
Python digital logic library
Harsh-Avinash/DLD-Lab-Simulations
CSE 1003 Digital Logic And Design's Lab Components all packed up in one neat and arranged repository
MohammadNiknam17/UART_Receiver_Transmitter_Controller_VHDL-FPGA
VHDL codes for UART Interface; hardware communication protocol. contains Receiver & Transmitter units & RAM memory.
PashaBarahimi/Digital-Logic-Design-Lab-Experiments
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
stineje/dldfall2023
This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.
arham2003/FAST-NUCES-Material
BS AI FAST NUCES Coursework material from 2022 - 2026. Access Course Outlines, Books, and Slides with ease.
bryan-hoang/elec-271-digital-systems-labs
VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.
H0NEYP0T-466/dld-workbench
⚡ A collection of Digital Logic Design (DLD) lab work and projects 🔌. Includes circuit designs, truth tables, simulations, and practical implementations. Covers core concepts of logic gates, combinational & sequential circuits, and hands-on problem-solving in digital systems.
L-I-M-I-T/DL_Piano
基于Nexys4开发板和PS2通信协议的键盘设计的电子琴，能够支持24个音阶的弹奏。
SiluPanda/8-bit-wallace-tree-multipier
This is a 8 bit binary number multiplier using wallace tree.
umarwaseeem/BS-CS-Semester-2
Semester 2 course material for BS Computer Science at Fast National University Of Computer And Emerging Sciences
anupbhowmik/Computer-Architecture-CSE-306
This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.
Danijel-Korent/homemade-CPU
designing a 8-bit CPU for fun
arhamhashmi01/RTL_Practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
ramiomer94/VLSI-design-projects
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
SarwanShah/8-bit-ALU-Using-Logic-Gates-2017
This project presents the hardware design for an 8-bit arithmetic logic unit