ShashankVM/generic_systemverilog_designs_library

A library of useful, fully parameterized RTL designs implemented in SystemVerilog.

binary_counter

n-bit binary counter with asynchronous reset in SystemVerilog.

binary_to_gray

n-bit binary to gray code combinational converter circuit in SystemVerilog.

demultiplexer

Demultiplexer of parameterized width and parameterized number of output ports.

full_adder

n-bit full adder in SystemVerilog

full_subtractor

n-bit full subtractor in SystemVerilog

gray_counter

n-bit gray code counter with asynchronous reset implemented using binary counter and binary to gray code combinational converter circuit in SystemVerilog.

multiplexer

Multiplexer of parameterized width and parameterized number of input ports.