functional-verification

nelsoncsc/easyUVM

A simple UVM example with DPI

rooinasuit/AXI_to_SPI

Designing means to communicate as an SPI master, being a part of AXI interface

JoseIuri/Simple_UVM

Implements a simple UVM based testbench for a simple memory DUT.

nelsoncsc/basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

fvutils/pyuvm-dataclasses

Apply dataclasses concept to testbench automation in Python

MarleyLobao/UVM_calculator

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

NikolaF-95/RAM_VIP

UVM VIP for Single Port RAM Synchronous Read/Write

nelsoncsc/basic_uvmc

A simple testbench with two refmods using UVM Connect

zuspec/zuspec-parser

Language parser

OmniaMohamed12/AES-128-Verification-Using-UVM

Verification of Advanced Encryption Standard (AES-128) Using UVM

OmniaMohamed12/S-AES-Design-and-Verification-using-SystemVerilog-and-UVM

Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.

PSSTools/psde

Provides Eclipse plug-ins for developing Accellera PSS

michellavezzo/clock_verilog

First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

OmniaMohamed12/apb-verification-uvm

Verification of Advanced Peripheral Bus (APB) protocol using the Universal Verification Methodology (UVM).

Pritam-Sethuraman/Calc1

reity/article-specifications-for-distinguishing-functions

This article presents a technique for assembling concise, lightweight specifications and unit tests for verifying the identity of a function; the technique sacrifices completeness to enable compact and portable specifications.