/S-AES-Design-and-Verification-using-SystemVerilog-and-UVM

Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.

Primary LanguageSystemVerilog

S-AES-Design-and-Verification-using-SystemVerilog-and-UVM

Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.

UVM Architecture

Copy of s aes uvm env - Page 1

Coverage Results

  • Functional Coverage:

    image

  • Code Coverage:

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Detailed coverage reports can be found in the sim directory, specifically in the code_cov_report.txt file and functional_cov_report.txt file.

Compilation and Simulation Steps

To compile the design and testbench, use the following command:

 vlog S_AES_Package.svh S_AES_Top.sv +cover

To simulate and run test with coverage analysis, use the following command:

vsim -batch S_AES_Top -coverage -do "run -all; coverage report -codeAll -cvg -verbose"