network-on-chip

sld-columbia/esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

ucb-bar/constellation

A Chisel RTL generator for network-on-chip interconnects

taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

aignacio/ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

agalimberti/NoCRouter

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

ic-lab-duth/NoCpad

HLS for Networks-on-Chip

jmjos/ratatoskr

Ratatoskr NoC Simulator

leds-lab/redscarf

System-on-Chip Interconnection Network - Simulation Environment (front-end)

timurkelin/simsimd

Development and simulation framework for Application Specific Vector Processor

zhipengzhaocmu/HLS_NoC

HLS code for Network on Chip (NoC)

ueqri/vis4mesh

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

Davxx/gem5_Garnet2.0_extensions

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

LamaNIkesh/MScFPGAStuff

My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

jyhuang91/flyover

A Voting Approach for Adaptive Network-on-Chip Power-Gating

egk696/InterChip_Bridge

A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

leds-lab/snocs

System-on-Chip Interconnect Network Simulation Environment back-end (simulator)

amamory/hermes-trojan

Example of hardware trojan in a router detected with formal property verification

chawki27000/retina-sim-old

Real-Time Network-on-chip Analysis and Simulation

egk696/InterNoC

A Network-on-Chip for the System-of-Systems Era, Enabling mixed interface communication between embedded devices (MCU, sensors etc.) over a common protcol stack

mohasnik/Network-On-Chip

RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.

amamory/hermes-router-axis-ip

A Vivado IP of Hermes network-on-chip router with AXI streaming interfaces

gabrielganzer/RTSNoC-Sniffer

Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.

amamory/hermes-2x2-noc-axis-ip

A 2x2 mesh NoC compatible with AXI streaming interface

amamory/hermes-noc-tester-vivado-ip

Vivado test IP for Hermes NoC Router

amamory/zynq-hermes-noc-demo

A demonstrator of Hermes network-on-chip communicating with the ARM processor

amamory/zynq-ps-hermes-noc

Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface

cnsl-nu/StocNoC-Accelerating-Stochastic-Models-Through-Reconfigurable-Network-on-Chip-Architectures

Reconfigurable network on chip architecture for accelerating stochastic models

hansikaweerasena/noxim

This is a fork of the Network on Chip Simulator - Noxim, enhanced with the capability to inject traffic traces from multiple in-order processors. The infrastructure and traffic injector can be extended to support more complex processors and traces.

Mobink980/Network-on-Chip

As we transition into the era characterized by many-core architectures and the challenges posed by dark silicon, the design and implementation of highly efficient on-chip interconnects have become paramount. This repository is dedicated to the advancement of efficient Network-on-Chip (NoC) solutions within the gem5 simulator framework.

RomeoMe5/circulantGraphs

Optimal circulant graphs generating results dataset

RomeoMe5/UOCNS-SE

UOCNS simulator in Spring enviroment

UFESL/.github

Introduction about Embedded systems lab, University of Florida

erwanregy/NoC-Simulation

Network-on-Chip Simulation using Noxim

projektjoe/Networks-On-Chip-Router-VHDL

RomeoMe5/GeNoC

GeNoC - Software implementation of the evolutionary computation method for the synthesis of quasi-optimal topologies for Networks-on-Chip