openlane-flow
There are 14 repositories under openlane-flow topic.
AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
ShonTaware/OpenSource_Physical_Design
This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
harshithsn/Universal-Shift-Register
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
CodePurble/sap
The SAP-1 in Verilog, and now as an ASIC!
krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
MayurTA/VSD-IAT_workshop
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
ShyamRazesh/DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)
arhamhashmi01/openlane-verification
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
muhammadtalhasami/openlane
This is my openlane repository in which we perform synthesis of our design/module.
Pa1mantri/CellDesign
Adding a Customized Standard Cell into the OpenLane Flow
Pa1mantri/VSDMemSOC
VSDMemSOC Implementation flow:: RTL2GDSII
SKpro-glitch/RISCV-Processor-ASIC
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
Pa1mantri/NASSCOM_SoC_Design
Complete RTL to GDSII flow of a picorv32a core
watbulb/tt-gds-macro-testing
TinyTapeout GDS blackbox macro testing