rtl-design
There are 47 repositories under rtl-design topic.
4xmen/Web-Package-RTL
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
4xmen/x-mega-menu
x mega menu is repsonsive mega menu based on vannilajs
4xmen/x-tree-select
Tree Select jQuery plugin
4xmen/rvnm
Responsive vertical navigation menu
pulp-platform/croc
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
snbk001/100DaysofRTL
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
Akashtailor-exe/30-days-of-verilog
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
synogate/gatery
Gatery, a library for circuit design.
maazm007/100Daysof_RTL
The Repository contains the code of various Digital Circuits
esynr3z/pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
AUCOHL/RTL-Repo
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
Abdelrahman1810/SPI_Slave_with_Single_Port_RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Luca-Dalmasso/DLX
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
Luca-Dalmasso/RISCV_LBIST
Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model
MohamedHussein27/RISC-V-Single-Cycle-Implementation
This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.
synogate/gatery_template
Template project for using gatery
alirezajaberirad/Object-Oriented-Modeling-of-Electronic-Circuits
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
cp024s/100-days-of-RTL
probable journey of RTL coding ft. Chandra Prakash
Farbod-Siahkali/Digital-Logical-Designs-Projects
Digital Logical Designs Course Projects
gabrielganzer/RTSNoC-Sniffer
Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.
Mhd-Shah/Verification-of-D--flipflop-using-UVM
Verification of D-FF using UVM on EDA playground
MohamedHussein27/AMPA_APB4_Protocol
This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime
williaml33moore/bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Ammar-Bin-Amir/ARTY_A7_I2C_MPU-6050
Integration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing
Ammar-Bin-Amir/AXI4
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
Ammar-Bin-Amir/I2C
RTL Design of Inter-Integrated Circuit
ammarmalik17/Verilog_Adders
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
farukyld/sort-circuit
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
Luca-Dalmasso/Max-Pooling_VHDL
HLSM with memory design for max pooling algorithm.
sidhantp1906/AMBA4-APB
Advanced Pheripheral Bus design using verilog HDL
SKpro-glitch/Parallel_Multiplier
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
ZAIN-ALI-02/UART
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
Khosravi19/SPA-CodeTime
Single-page application of programming courses using React with a panel and login page
shahed22/Dadda-8-bit
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
mrxeg1995/yanbu
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