farukyld/sort-circuit

Issues

• change arithmetic units with their synthesizable equivslents

  #56 opened a year ago by farukyld
  0

• Add Information into README File About How to Experiment with the Verilog Codes

  #55 opened a year ago by farukyld
  0

• Test Verilog Codes

  #53 opened a year ago by farukyld
  0

• Write Verilog Codes

  #50 opened a year ago by farukyld
  0

• test and fix bugs in the circuits

  #45 opened a year ago by farukyld
  2

• Modifiy the Controller and Datapath modules to Use the Write Submodule

  #40 opened a year ago by farukyld
  1

• Connect the Circuit into a Test Environment and Test

  #8 opened a year ago by farukyld
  3

• Implement an AXI-Lite Write Submodule

  #32 opened a year ago by farukyld
  1

• Implement a Memory Filler

  #31 opened a year ago by farukyld
  0

• Implement a Register File That the Circuit Can Communicate with

  #6 opened a year ago by farukyld
  5

• Update the Datapath and Controller Declaration. According to HLSM

  #12 opened a year ago by farukyld
  0

• Create the State Table

  #13 opened a year ago by farukyld
  2

• Implement Datapath

  #15 opened a year ago by farukyld
  2

• Implement the Controller

  #16 opened a year ago by farukyld
  3

• Add Internal Control Signals and Register to Handle Return State to the Controller

  #21 opened a year ago by farukyld
  0

• Add ld_return_read_data Control Signal between Controller and Datapath

  #17 opened a year ago by farukyld
  0

• Implement the Controller and the Datapath

  #5 opened a year ago by farukyld
  1

• Draw the State Diagram of the HLSM

  #2 opened a year ago by farukyld
  1

• Draw the State Diagram of the FSM

  #3 opened a year ago by farukyld
  1

• Specify the Inputs-Outputs-Registers of the Datapath and the Controller

  #4 opened a year ago by farukyld
  4

• Determine the Communication Protocol between Register File and the Circuit

  #7 opened a year ago by farukyld
  2

• Write C Code

  #1 opened a year ago by farukyld
  0