sdram-controller
There are 17 repositories under sdram-controller topic.
PrimeMHD/FPGA_ThreeLevelStorage
【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
AngeloJacobo/FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
yigitbektasgursoy/SDRAM_Verilog
Verilog HDL implementation of SDRAM controller and SDRAM model
MinatsuT/CYC1000_SDRAM
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
Arkowski24/sdram-controller
Simple SDRAM Controller for DE10-Lite.
cw1997/SDRAM-Controller
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
jakubcabal/sdram-tester-fpga
SDRAM Tester implemented in FPGA
egk696/EDAC_SDRAM_Controller
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
agg23/sdram-controller
A HDL SDRAM controller designed for retro hardware and FPGAs
ShwetaKiranTotla/Micro-processor-Design-Verification
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
armleo/sdram_controller
SDR SDRAM Controller with Avalon-MM bus; [Bugged, deprecated]
kevin861222/SDRAM_controller
SDRAM controller
oskarwires/sdram_controller
High-Speed SystemVerilog SDRAM Controller
teekamkhandelwal/SRAM_Controller
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
yasnakateb/SdramController
🛠 A SDRAM controller in Verilog HDL
Nikhil-Ashok-Kumbhar/SDRAM-Controller-Design
Overview: The goal of this project is to design an SDRAM controller that allows SDRAM memory to be interfaced with a microprocessor having only asynchronous memory support. There is no requirement to build the hardware, but a complete written report containing schematics and theory of operation is required