tristynferreiro/ISD-PO
A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
VHDL
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A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
VHDL
No one’s star this repository yet.