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ultraembedded
/
core_usb_fs_phy
USB Full Speed PHY
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Verilog
GNU Lesser General Public License v2.1
LGPL-2.1
core_usb_fs_phy GitHub
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Open issue
Latch inferred for signal `\usb_transceiver.\out_dp'
#1 opened
4 years ago
by
tambewilliam
0