Pinned Repositories
cosim
Interfacing VHDL and foreign languages with VUnit
doit
task management & automation tool
gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
hwstudio
GUI editor for hardware description designs
issue-runner
Execute Minimal Working Examples (MWEs) defined in the body of Markdown files or GitHub issues.
osvb
Open Source Verification Bundle for VHDL and System Verilog
SIEAV
Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
umarcor
VHDLNumericUserGuides
vunit-cosim
umarcor's Repositories
umarcor/osvb
Open Source Verification Bundle for VHDL and System Verilog
umarcor/hwstudio
GUI editor for hardware description designs
umarcor/SIEAV
Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
umarcor/umarcor
umarcor/gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
umarcor/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
umarcor/fomu-workshop
Support files for participating in a Fomu workshop
umarcor/ghdl-language-server
Language server based on ghdl
umarcor/cobra
A Commander for modern Go CLI interactions
umarcor/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
umarcor/f4pga
Documentation for F4PGA
umarcor/f4pga-examples
Example designs showing different ways to use SymbiFlow toolchains.
umarcor/f4pga-website
umarcor/ghdl
VHDL 2008/93/87 simulator
umarcor/ghdl-cosim
umarcor/ghdl-extended-tests
umarcor/godot-build-containers
Godot engine build containers
umarcor/godot-docs
Godot Engine official documentation
umarcor/html5liburua
HTML5-en inguruko liburuaren kode biltegia
umarcor/MINGW-packages
Package scripts for MinGW-w64 targets to build under MSYS2.
umarcor/neorv32
A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
umarcor/neorv32-setups
:file_folder: Exemplary NEORV32 setups for various FPGA boards and toolchains.
umarcor/osvvm.github.io
HTML Docs for OSVVM
umarcor/OsvvmLibraries
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
umarcor/rticles
LaTeX Journal Article Templates for R Markdown
umarcor/setup-ghdl-ci
JavaScript action for users to easily install nightly GHDL assets in GitHub Actions workflows
umarcor/towncrier
Manage the release notes for your project.
umarcor/Unike267-Ejercicios-Cosimulacion
Repositorio donde se mostrará los ejerciocios realizados para la asignatura "cosimulación para la verificación de sistemas sobre FPGAs".
umarcor/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
umarcor/yosys
Yosys Open SYnthesis Suite