usmanali-rs

micro_benchmark

Micro Benchmarks for FPGA design verification

APB_Slave

APB slave with a memory module as peripheral

Design-Verifcation-Environment-for-AHBlite-Slave

Design Verification Environment is used to check the functional correctness of the Design Under Test (DUT) by generating and driving a predefined input sequence to a design, capturing the design output and comparing with-respect-to expected output. Verification environment is a group of classes or components. where each component is performing a specific operation. i.e, generating stimulus, driving, monitoring, etc. and those classes will be named based on the operation.

RISCV_Processor

sail-riscv

Sail RISC-V model

usmanali-rs/APB_Slave

APB slave with a memory module as peripheral

usmanali-rs/Design-Verifcation-Environment-for-AHBlite-Slave

Design Verification Environment is used to check the functional correctness of the Design Under Test (DUT) by generating and driving a predefined input sequence to a design, capturing the design output and comparing with-respect-to expected output. Verification environment is a group of classes or components. where each component is performing a specific operation. i.e, generating stimulus, driving, monitoring, etc. and those classes will be named based on the operation.

usmanali-rs/RISCV_Processor

usmanali-rs/sail-riscv

Sail RISC-V model