vaughnbetz/COFFE

Issues

• Analytical method for FPGA evaluation

  #59 opened 4 months ago by ketan170102030
  0

• HSPICE failed to run while updating delay for sb_mux

  #58 opened 6 months ago by ketan170102030
  3

• About the meaning of lut_input, the composition of a tile and how to measure the power consumption of a tile.

  #50 opened a year ago by luck-codeer
  2

• About [R, C] in the metal layer

  #53 opened a year ago by luck-codeer
  5

• Failed to update delay(hspice failed to run)

  #57 opened a year ago by YY246
  1

• Is the COFFE run in linux?

  #56 opened a year ago by YY246
  0

• About the issue of abnormal power consumption evaluation at low temperatures

  #55 opened a year ago by luck-codeer
  6

• How to compute the "LocalRoutingWireLoad"

  #54 opened a year ago by narutozxp
  3

• VPR failed when running with the architecture description file that comes with VTR in COFFE_22nm

  #52 opened a year ago by luck-codeer
  0

• About the meaning of crit_path_delay

  #51 opened a year ago by luck-codeer
  1

• About an error(HSPICE failed to run)When I run an example (flut0. yaml).

  #43 opened a year ago by luck-codeer
  7

• Question about whether COFFE supports energy_per_toggle in the architecture description file required for VTR

  #49 opened a year ago by jdzhu19
  5

• About the architecture description xml file exported by COFFE cannot be synthesized by OdinII in VTR

  #44 opened a year ago by jdzhu19
  10

• Question about the Tdel generated by COFFE

  #48 opened a year ago by jdzhu19
  0

• A question about the COFFE version used for the architecture generated by COFFE in VTR

  #45 opened 2 years ago by jdzhu19
  0

• Innovs PnR runtime needs express option to reduce QoR and reduce runtime

  #47 opened 2 years ago by StephenMoreOSU
  0

• About the minimum supported temperature of COFFE2

  #46 opened 2 years ago by luck-codeer
  3

• About running COFFE with local optimization instead of global

  #40 opened 2 years ago by yc2367
  13

• About employing diffusion sharing for multi-input gates like nand2 nor2.

  #39 opened 2 years ago by yc2367
  1

• About wordlinedriver area calculation in fpga.py

  #36 opened 2 years ago by yc2367
  6

• Inconsistency with area and delay cost factors

  #32 opened 4 years ago by aman26kbm
  4

• lut connection in the generated xml file

  #29 opened 4 years ago by Alimellat
  2

• vtr arch.xml file does not adapt to at least some non-default COFFE settings

  #30 opened 4 years ago by vaughnbetz
  0

• Data port declarations in XML

  #27 opened 4 years ago by Alimellat
  6

• COFFE should check for unsupported LUT sizes in the input files.

  #26 opened 4 years ago by vaughnbetz
  0

• RAM block architecture parameters should be echoed back by COFFE

  #25 opened 4 years ago by vaughnbetz
  0

• Bug at Finfet Case

  #20 opened 5 years ago by basakozaydin
  2

• Refactor Finfet support code to reduce duplication and support all features

  #23 opened 5 years ago by vaughnbetz
  1

• Merge alternative LUT design support into COFFE master

  #22 opened 5 years ago by vaughnbetz
  0

• Port transmission gate per circuit element (LUT vs. routing) into COFFE master

  #21 opened 5 years ago by vaughnbetz
  0

• In flut mux simulation why is the delay measured from the flut input to the carry chain mux output?

  #19 opened 6 years ago by MohamedEldafrawy
  2

• Wrong simulation for connection block

  #18 opened 6 years ago by MohamedEldafrawy
  2

• Not getting correct area and delay with initial sizes and --no_sizing

  #13 opened 10 years ago by LindaLS
  0

• Final lut delay is negative, nothing prior to that was...

  #14 opened 10 years ago by LindaLS
  1

• Representative delay does not reflect sub-circuit delays?

  #15 opened 10 years ago by LindaLS
  0

• Add restorer lengths and include them when sizing

  #16 opened 10 years ago by LindaLS
  0

• Delay change after updating delay?

  #17 opened 10 years ago by LindaLS
  0

• Index error creating list of t_rise_fall

  #9 opened 10 years ago by LindaLS
  1

• Negative delays

  #11 opened 10 years ago by LindaLS
  0

• Large inverter sizes when unable to equalize rise/fall

  #12 opened 10 years ago by LindaLS
  1

• Handing when HSPICE simulation failed

  #1 opened 10 years ago by LindaLS
  0

• Empty parameter_dict.keys() causing oob error

  #2 opened 10 years ago by LindaLS
  0

• Invalid index when searching for best index

  #3 opened 10 years ago by LindaLS
  0

• Index at -1, but not causing any problems

  #4 opened 10 years ago by LindaLS
  1

• Invalid index when creating list of tfall_trise

  #5 opened 10 years ago by LindaLS
  0

• key error, transistor_sizes[tgate_lut_L1] not found

  #7 opened 10 years ago by LindaLS
  2

• tgate still using ptran's length and width

  #6 opened 10 years ago by LindaLS
  0

• Update area calculation for transmission gates

  #8 opened 10 years ago by LindaLS
  0

• Change --use_tgate option to a flag

  #10 opened 10 years ago by charleschiasson
  1