vborchsh

vborchsh's Stars

• sympy/sympy

  A computer algebra system written in pure Python

  Language:Python13k29113.4k4.5k

• pufferffish/wireproxy

  Wireguard client that exposes itself as a socks5 proxy

  Language:Go4.5k2590272

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.9k134722531

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.6k723.6k616

• ghdl/ghdl

  VHDL 2008/93/87 simulator

  Language:VHDL2.4k1012.2k366

• jameskokoska/Cashew

  💸 An app created to help users manage a budget and purchases

  Language:Dart1.9k24468252

• nodejs/llhttp

  Port of http_parser to llparse

  Language:TypeScript1.7k42145187

• AndreyAkinshin/Russian-Phd-LaTeX-Dissertation-Template

  LaTeX-template for russian Phd thesis

  Language:TeX1.3k73205676

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog8705157275

• amaargiru/pycore

  Python Extended Cheatsheet. I'm using this repository to chronicle my journey through Python.

  Language:Jupyter Notebook50025279

• RedPitaya/RedPitaya

  Red Pitaya Ecosystem and Applications

  Language:C48794206632

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog3631639105

• EvgenyNerush/easy-xray

  Script for Linux which makes XRay installation and configuration easy

  Language:Shell23371830

• alexforencich/cocotbext-axi

  AXI interface modules for Cocotb

  Language:Python214136870

• catkira/open5G_phy

  A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

  Language:Jupyter Notebook193131530

• mustafabbas/ECE1373_2016_hft_on_fpga

  High Frequency Trading using Vivado HLS

  Language:Verilog1205232

• catkira/py3gpp

  A Python package for 5G-NR simulations

  Language:Python98101718

• bb16177/OTFS-Simulation

  A simulation of a wideband wireless communications system with multipath fading for OFDM and OTFS

  Language:MATLAB943128

• Alga53/DISMMSE-Turbo-Equalizer-for-OTFS

  This repo contains simulation code for DI-S-MMSE Turbo Equalizer and LMMSE Equalizer applied to OTFS Modulation.

  Language:MATLAB47208

• chili-chips-ba/wireguard-fpga

  Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

  Language:VHDL348100

• avashist003/UVM_Verification

  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence

  Language:SystemVerilog282111

• mxg/topaz

  Language:SystemVerilog143

• zilligm/py3gppchannels

  The py3gppchannels library is a Python package that implements the 3GPP standardized radio channel models (3GPP TR 38.901). It provides a comprehensive set of functions for simulating wireless communication systems and evaluating their performance under realistic channel conditions.

  Language:Python83

• esynr3z/svjson

  🇯 JSON encoder and decoder in pure SystemVerilog

  Language:SystemVerilog61100

• esynr3z/pip-hdl

  📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

  Language:Python520

• stjaeckel/QuaDRiGa-NG

  QuaDRiGa, short for QUAsi Deterministic RadIo channel GenerAtor, is used for generating realistic radio channel impulse responses for system-level simulations of mobile radio networks.

  Language:MATLAB5300

• kkurenkov/uvm-empty-project

  generator for verification environment

  Language:SystemVerilog4100

• yuravg/color_questasim

  A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

  Language:Perl4100

• RedPitaya/scpi-parser

  Open Source SCPI device library

  Language:C32010

• punzik/simbench

  Simple HDL simulators benchmark

  Language:Verilog2100