Pinned Repositories
battleship
Battleship in C++
cgra-systemc
SystemC implementation of a parameterizable CGRA
cgra_assembler
Small assembler to create VCGRA machine code from textual description.
freebsd
FreeBSD src tree (read-only mirror)
gsysc
Upgrade from qt3 and SystemC 2.0 to qt5 and SystemC 3.0
gsysc-testproject
Verify functionality of gSysC library.
How-to-Make-a-Computer-Operating-System
How to Make a Computer Operating System in C++
mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures
meta-adi
This is the Analog Devices Inc. Yocto/OpenEmbedded layer
task-graph-simulation-builder
SystemC simulator of a CGRA architecture
werneazc's Repositories
werneazc/gsysc
Upgrade from qt3 and SystemC 2.0 to qt5 and SystemC 3.0
werneazc/cgra-systemc
SystemC implementation of a parameterizable CGRA
werneazc/task-graph-simulation-builder
SystemC simulator of a CGRA architecture
werneazc/battleship
Battleship in C++
werneazc/cgra_assembler
Small assembler to create VCGRA machine code from textual description.
werneazc/freebsd
FreeBSD src tree (read-only mirror)
werneazc/gsysc-testproject
Verify functionality of gSysC library.
werneazc/How-to-Make-a-Computer-Operating-System
How to Make a Computer Operating System in C++
werneazc/mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures
werneazc/meta-adi
This is the Analog Devices Inc. Yocto/OpenEmbedded layer
werneazc/task-graph-simulation-library
Library of CGRA Components for Task-Graph-Simulation-Builder
werneazc/task-vertex-generator
Generator for new Processing Elements in CGRA Task-Graph-Simulator