Your one-stop shop for all fpga programs- in your favourite language-->Python
- Ripple Carry Adder
- Carry Look Ahead Adder
- Carry skip Adder
- BCD Additon
- BCD Subtraction
- Array Multiplication(Unsigned Multiplier 4-bit)
- Magnitude Comparator
- LINEAR FEEDBACK SHIFT REGISTER (LSFR)
- UNIVERSAL SHIFT REGISTER
- 8- BIT PARITY GENERATOR
- 3-BIT ARBITRARY COUNTER
- SEQUENCE DETECTOR-DESIGN OF SEQUENCE DETECTOR(11101) WITH AND WITHOUT OVERLAPPING USING MOORE STATE MACHINE
- SEQUENCE DETECTOR- DESIGN OF SEQUENCE DETECTOR WITH AND WITHOUT OVERLAPPING USING MEALY STATE MACHINE
- FIRST IN FIRST OUT (FIFO)
Convert all verilog files from here to myHDL here with proper Documentation. More verilog and VHDL files will be added here
MIT License. You are free to copy and reuse the code.