Pinned Repositories
FPGA_Based_CNN
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
regex_coprocessor
An accelerator to which you can offload RE matching and that does not use backtracking
verilog-ethernet
Verilog Ethernet components for FPGA implementation
x-ui-yg
x-ui精简修改版脚本，集成argo隧道，默认节点即可解锁ChatGPT，xray配置已添加支持warp-socks5与wireguard warp出站分流，实现多IP出站分流共存
wudinine's Repositories
wudinine/x-ui-yg
x-ui精简修改版脚本，集成argo隧道，默认节点即可解锁ChatGPT，xray配置已添加支持warp-socks5与wireguard warp出站分流，实现多IP出站分流共存
wudinine/FPGA_Based_CNN
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
wudinine/regex_coprocessor
An accelerator to which you can offload RE matching and that does not use backtracking
wudinine/verilog-ethernet
Verilog Ethernet components for FPGA implementation