wudinine

wudinine's Stars

• hq450/fancyss_history_package

  科学上网插件的离线安装包储存在这里

  10.3k43603.6k

• yonggekkk/x-ui-yg

  x-ui精简修改版脚本，支持alpine系统，集成argo固定临时双隧道（可共存），支持部分节点聚合订阅、sing-box订阅、clash-meta订阅的配置输出

  Language:Shell1.6k2345677

• awai54st/PYNQ-Classification

  Python on Zynq FPGA for Convolutional Neural Networks

  Language:Jupyter Notebook5993583217

• QShen3/CNN-FPGA

  使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

  Language:Verilog47794107

• hunterlew/convolution_network_on_FPGA

  CNN acceleration on virtex-7 FPGA with verilog HDL

  Language:Verilog3982319130

• efabless/raven-picorv32

  Silicon-validated SoC implementation of the PicoSoc/PicoRV32

  Language:Verilog25432764

• AniketBadhan/Convolutional-Neural-Network

  Implementation of CNN using Verilog

  Language:Verilog1748875

• mtmd/FPGA_Based_CNN

  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

  Language:Verilog16915378

• sumanth-kalluri/cnn_hardware_acclerator_for_fpga

  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

  Language:Verilog1545850

• alan4186/Hardware-CNN

  A convolutional neural network implemented in hardware (verilog)

  Language:Verilog14918984

• diaoenmao/FPGA-CNN

  FPGA implementation of Cellular Neural Network (CNN)

  Language:Verilog13327083

• ilaydayaman/CNN_for_SLR

  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

  Language:Verilog845330

• cc1024/Google

  收集一些Google镜像

  28506

• g0kul/vcnn

  Verilog Convolutional Neural Network on PYNQ

  Language:VHDL273212

• gr-rahimi/APSim

  Language:Python23407

• brianhill11/FPGA-CNN

  This repo is for ECE44x (Fall2015-Spring2016)

  Language:SystemVerilog194014

• suhasr1991/Convolutional-Neural-Network-hardware-using-Verilog

  A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers. Sigmoid case statement was also implemented in verilog to get the sigmoid values for intermediate outputs in a layer. This design was simulated and synthesized at 50 MHz on Quartus Prime 17.0. The FPGA family was Cyclone V. Total logic elements used were 724, total bits used 121856(only 50% use of memory).

  Language:Verilog15006

• wudinine/x-ui-yg

  x-ui精简修改版脚本，集成argo隧道，默认节点即可解锁ChatGPT，xray配置已添加支持warp-socks5与wireguard warp出站分流，实现多IP出站分流共存

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