Pinned Repositories
BmpHandleVerilog
BMP file handling Verilog tasks
caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
e200_opensource
The Ultra-Low Power RISC Core
OPENSTA
git@github.com:abk-openroad/OpenSTA.git
simple_reg_model
System verilog register model for uvm testbenches.
verilator
clone from git@github.com:poucotm/verilator.git
wxz1003083273's Repositories
wxz1003083273/BmpHandleVerilog
BMP file handling Verilog tasks
wxz1003083273/caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
wxz1003083273/e200_opensource
The Ultra-Low Power RISC Core
wxz1003083273/OPENSTA
git@github.com:abk-openroad/OpenSTA.git
wxz1003083273/simple_reg_model
System verilog register model for uvm testbenches.
wxz1003083273/verilator
clone from git@github.com:poucotm/verilator.git