wxz1003083273

wxz1003083273's Stars

• openai/CLIP

  CLIP (Contrastive Language-Image Pretraining), Predict the most relevant text snippet given an image

  Language:Jupyter Notebook23.8k3173883.1k

• mahmoud/awesome-python-applications

  💿 Free software that works great, and also happens to be open-source Python.

  Language:Jupyter Notebook16.4k756762.7k

• PySimpleGUI/PySimpleGUI

  Python GUIs for Humans! PySimpleGUI is the top-rated Python application development environment. Launched in 2018 and actively developed, maintained, and supported in 2024. Transforms tkinter, Qt, WxPython, and Remi into a simple, intuitive, and fun experience for both hobbyists and expert users.

  Language:Python13.3k2303.6k1.8k

• ParthJadhav/Tkinter-Designer

  An easy and fast way to create a Python GUI 🐍

  Language:Python8.7k87271801

• doxygen/doxygen

  Official doxygen git repository

  Language:C++5.5k1517.7k1.3k

• biobootloader/wolverine

  Language:Python5.2k8825519

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala3.8k1511k579

• modelscope/swift

  ms-swift: Use PEFT or Full-parameter to finetune 300+ LLMs or 50+ MLLMs. (Qwen2, GLM4v, Internlm2.5, Yi, Llama3.1, Llava-Video, Internvl2, MiniCPM-V, Deepseek, Baichuan2, Gemma2, Phi3-Vision, ...)

  Language:Python2.5k20706229

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.3k3756179

• bespoke-silicon-group/basejump_stl

  BaseJump STL: A Standard Template Library for SystemVerilog

  Language:SystemVerilog4782818295

• rmcantin/bayesopt

  BayesOpt: A toolbox for bayesian optimization, experimental design and stochastic bandits.

  Language:C++391242892

• pulp-platform/pulpissimo

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  Language:SystemVerilog36444312159

• chipsalliance/Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++3432691367

• pulp-platform/riscv-dbg

  RISC-V Debug Support for our PULP RISC-V Cores

  Language:SystemVerilog200207071

• NaturalDocs/NaturalDocs

  Natural Docs source code documentation system

  Language:C#193198733

• taichi-ishitani/tnoc

  Network on Chip Implementation written in SytemVerilog

  Language:SystemVerilog145134042

• sifive/fpga-shells

  Language:Scala13244964

• freechipsproject/diagrammer

  Provides dot visualizations of chisel/firrtl circuits

  Language:Scala113171620

• pulp-platform/pulp-sdk

  Language:C98197573

• ovh/sv2chisel

  (System)Verilog to Chisel translator

  Language:Scala9718810

• pcie-bench/pcie-model

  Language:Python519212

• MikePopoloski/pyslang

  Python bindings for slang, a library for compiling SystemVerilog

  Language:Python383376

• wyvernSemi/usbModel

  USB virtual model in C++ for Verilog

  Language:C++25503

• merledu/TileLink

  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

  Language:Scala194159

• recogni/svlib

  svlib from http://www.verilab.com/resources/svlib/

  Language:SystemVerilog19406

• yvnr4you/SDRAM-Verification

  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by Dinesh in Opencores.org

  Language:Verilog152011

• opensocdebug/osd-sw

  Open SoC Debug Software reference implementation

  Language:C47136

• huginexpert/RHugin

  RHugin is a middleware making it possible to Create Bayesian Networks from the R Programming Language. RHugin is a middleware exposing the HUGIN API to any program written in R. RHugin was originally created by Kjell Konis (kjellpk) but is currently maintained by Hugin Expert.

  Language:C21

• ktbarrett/scdil

  simple configuration and data interchange language

  Language:Python1100

• rswarbrick/acov

  Generator of functional coverage tracking code for Verilog projects

  Language:Haskell1102