Pinned Repositories
2021-LPCVC-Referee
The evaluation system (referee) for the 2020 Low Power Computer Vision Challenge.
32_bit_MIPS_Pipeline_Datapath_Simulation
Computer Architecture Project - Understand how the process of execution of the machine code in the MIPS pipelined data path takes place.
ai-accelerators
CSV spreadsheets and other material for AI accelerator survey papers
AIdea-FPGA-Edge-AI
Sample code for AIdea FPGA Edge AI – AOI Defect Classification competition
asl_tutorial
Tutorials based on the ASL (American Sign Language) dataset
astyx-vis
visualization of ASTYX automotive dataset (radar/lidar/camera)
awesome-radar-perception
A curated list of radar datasets, detection, tracking and fusion
aws-cloud-and-xilinx-workshop
DNNDK_Installation
This is a tutorials to quickly install DNNDK, Caffe and TensorFlow.
Ultra96v2-DPU
DPU Integration for Ultra96v2
xelalin's Repositories
xelalin/DNNDK_Installation
This is a tutorials to quickly install DNNDK, Caffe and TensorFlow.
xelalin/2021-LPCVC-Referee
The evaluation system (referee) for the 2020 Low Power Computer Vision Challenge.
xelalin/32_bit_MIPS_Pipeline_Datapath_Simulation
Computer Architecture Project - Understand how the process of execution of the machine code in the MIPS pipelined data path takes place.
xelalin/ai-accelerators
CSV spreadsheets and other material for AI accelerator survey papers
xelalin/AIdea-FPGA-Edge-AI
Sample code for AIdea FPGA Edge AI – AOI Defect Classification competition
xelalin/asl_tutorial
Tutorials based on the ASL (American Sign Language) dataset
xelalin/astyx-vis
visualization of ASTYX automotive dataset (radar/lidar/camera)
xelalin/awesome-radar-perception
A curated list of radar datasets, detection, tracking and fusion
xelalin/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
xelalin/fmcw-1
6GHz frequency-modulated continuous-wave radar with real-time range detection
xelalin/fpga_craft
A voxel game/Minecraft clone for the iCE40 UP5K FPGA
xelalin/FpOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
xelalin/glow
Compiler for Neural Network hardware accelerators
xelalin/hardh264
A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
xelalin/I.IMX8_Thor96
Arrow Global solution based on iMX8M MPU for Human Machine Interface Applications
xelalin/ITRI-OpenDLA
OpenDLA for trying the demo and FPGA solution
xelalin/kr260_robotic_arm
A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit.
xelalin/MaaXBoard-RT-V3--Projects
xelalin/open-nic-shell
xelalin/PicoEVB
Public repository for PicoEVB (Xilinx Artix XC7A50T based)
xelalin/radar_dataset_astyx
xelalin/soDLA
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
xelalin/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
xelalin/tensil
Open source machine learning accelerators
xelalin/Vitis-AI-DPU_TRD-for-ZCU106
Port of the ZCU104_dpu Vitis Platform to the ZCU106 with instructions to build Vitis DPU_TRD
xelalin/Vitis-In-Depth-Tutorial
xelalin/vitis_ai_custom_platform_v1.2.1
xelalin/xup_vitis_network_example
VNx: Vitis Network Examples
xelalin/yolor
implementation of paper - You Only Learn One Representation: Unified Network for Multiple Tasks (https://arxiv.org/abs/2105.04206)
xelalin/yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard