xiaoyu1004

xiaoyu1004's Stars

• naklecha/llama3-from-scratch

  llama3 implementation one matrix multiplication at a time

  Language:Jupyter Notebook13.2k1.1k

• microsoft/AI-System

  System for AI Education Resource.

  Language:Python3.5k431

• Bruce-Lee-LY/flash_attention_inference

  Performance of the C++ interface of flash attention and flash attention v2 in large language model (LLM) inference scenarios.

  Language:C++202

• karpathy/llama2.c

  Inference Llama 2 in one file of pure C

  Language:C17.3k2.1k

• ggerganov/llama.cpp

  LLM inference in C/C++

  Language:C++65.9k9.5k

• THU-DSP-LAB/ventus-gpgpu-verilog

  GPGPU supporting RISCV-V, developed with verilog HDL

  Language:Verilog5910

• Dao-AILab/flash-attention

  Fast and memory-efficient exact attention

  Language:Python13.7k1.3k

• raphaelmeyer/pickle-cpp

  Language:C++1

• vllm-project/vllm

  A high-throughput and memory-efficient inference and serving engine for LLMs

  Language:Python28k4.1k

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7k522

• Jerc007/Open-GPGPU-FlexGrip-

  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation

  Language:VHDL8218

• ROCm/ROCm-ComputeABI-Doc

  ROCm - AMDGPU Compute Application Binary Interface

  4012

• ROCm/LLVM-AMDGPU-Assembler-Extra

  LLVM AMDGPU Assembler Helper Tools

  Language:CMake11016

• feifei14119/rocm_start_sample

  hip rocm start sample for amd gpu

  Language:C++52

• FlippingLogic/fpga_read_bram

  Read FPGA bram content and transfer data to PC through Uart.

  Language:Verilog2

• WangXuan95/FPGA-UART

  Include 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

  Language:Verilog10422

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.8k647

• THU-DSP-LAB/ventus-gpgpu-cpp-simulator

  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus

  Language:C191

• PawelPerek/eeric

  A online RISC-V simulator with vector instructions support

  Language:Rust43

• light-ly/chisel-template

  自建 chisel 工程模板

  Language:Scala105

• github-3rr0r/RV32ISC

  A RISC-V RV32I ISA Single Cycle CPU

  Language:Scala204

• debtanu09/systolic_array_matrix_multiplier

  This is a verilog implementation of 4x4 systolic array multiplier

  Language:Verilog349

• XinyiYuan/Computer_Architecture

  大三上计算机体系结构研讨课 源代码

  Language:Verilog31

• NVIDIA/cub

  [ARCHIVED] Cooperative primitives for CUDA C++. See https://github.com/NVIDIA/cccl

  Language:Cuda1.7k447

• hughperkins/VeriGPU

  OpenSource GPU, in Verilog, loosely based on RISC-V ISA

  Language:SystemVerilog78990

• prajna-lang/prajna

  a program language for AI infrastructure

  Language:C++8712

• Multi2Sim/m2s-bench-amdsdk-2.5-src

  AMD Software Development Kit 2.5 Sources

  Language:C++85

• scratch-gpu/MIAOW2

  MIAOW2.0 FPGA implementable design

  106

• ROCm/HIP

  HIP: C++ Heterogeneous-Compute Interface for Portability

  Language:C++3.7k528

• THU-DSP-LAB/ventus-gpgpu-doc

  documentation for ventus gpgpu

  153