xupgit/High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
VHDL
Stargazers
- anilcelebiKocaeli University
- beihaixingchen
- bjrjkSKLP, ICT, CAS
- blurSong
- Busy-Bob
- cccisi@UCAS
- cctt1014Singapore
- chaosu-zdZD automotive GmbH @ZDAutomotive
- Cu1Ao无
- DaichouNational Chiao Tung University (NCTU)
- derange-alembic
- FredKellerman
- JS00000
- kaoruzhu1NONE
- KevinLvLight
- kim-sunghoon
- lishen565
- liubenyuanXi'an
- lizibo66
- meicale瑞雪兆丰念
- mengshus
- nulidangxueshenQinghai University
- pphuthGermany
- shdyna
- sinaasadiyan
- tbh111DLUT-UCAS
- thulasiramvarma
- varunnagpaal
- weixinlHaian
- wuyasheng
- wxbbuaa2011UCAS
- xiechen7Toronto
- XS30
- yjg0821
- YouliangJiangTencent
- youtuo123