xver

xver's Stars

• TheAlgorithms/Python

  All Algorithms implemented in Python

  Language:Python184k5.9k1.5k44.3k

• ByteByteGoHq/system-design-101

  Explain complex systems using visuals and simple terms. Help you prepare for system design interviews.

  63.1k812486.6k

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.5k1056.7k745

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.5k703.5k584

• olofk/fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

  Language:Python1.2k65389242

• renatoGarcia/icecream-cpp

  🍦 Never use cout/printf to debug again

  Language:C++55791929

• mariusmm/RISC-V-TLM

  RISC-V SystemC-TLM simulator

  Language:C269181471

• zeroasiccorp/logik

  A configurable RTL to bitstream FPGA toolchain

  Language:Python251717

• NaturalDocs/NaturalDocs

  Natural Docs source code documentation system

  Language:C#195198733

• avidan-efody/wave_rerunner

  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

  Language:Python51427

• MikePopoloski/pyslang

  Python bindings for slang, a library for compiling SystemVerilog

  Language:Python433387

• aristanetworks/ctypegen

  Generate ctypes boilerplate code from debugging information; Use python to mock C code for testing

  Language:Python2811710

• AsFigo/apb_uvc_verilator

  APB UVC ported to Verilator

  Language:SystemVerilog11203

• mkohler/cython_swig

  Language:C8504

• intel/rohd-wave-viewer

  Language:Dart71