yvantor

yvantor's Stars

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog8k7225609

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.7k1371.8k918

• The-OpenROAD-Project/OpenROAD-flow-scripts

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  Language:Verilog38612441316

• pulp-platform/cheshire

  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

  Language:Verilog232152655

• XUANTIE-RV/riscv-matrix-extension-spec

  A matrix extension proposal for AI applications under RISC-V architecture

  Language:Makefile129111324

• pulp-platform/carfield

  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

  Language:Tcl83124516

• pulp-platform/pulp-runtime

  Simple runtime for Pulp platforms

  Language:C4261036

• pulp-platform/axi-io-pmp

  Input / Output Physical Memory Protection Unit for RISC-V

  Language:SystemVerilog8512

• fischeti/WRapped

  Wrapped, but for Weekly Reports

  Language:Rust6201

• pulp-platform/astral

  A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

  Language:Tcl6133

• pulp-platform/InjectaFault

  Language:Tcl6402

• adam-maj/tt06

  Language:Verilog2201