zhuguiyuan

zhuguiyuan's Stars

• zephyrproject-rtos/zephyr

  Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

  Language:C10.5k40422.4k6.4k

• riscv-software-src/riscv-isa-sim

  Spike, a RISC-V ISA Simulator

  Language:C2.4k130834826

• remzi-arpacidusseau/ostep-homework

  Language:Python2k1726953

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1k39118252

• belaban/JGroups

  The JGroups project

  Language:Java1k930475

• YosysHQ/oss-cad-suite-build

  Multi-platform nightly builds of open source digital design and verification tools

  Language:Shell784288971

• karlrupp/microprocessor-trend-data

  Data repository for my blog series on microprocessor trend data.

  Language:Gnuplot49849978

• WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial

  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

  Language:Batchfile40811482

• milkv-duo/duo-buildroot-sdk

  Milk-V Duo Official buildroot SDK

  Language:C3871595168

• pulp-platform/ara

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

  Language:C35022181124

• UCSBarchlab/PyRTL

  A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

  Language:Python2532523576

• cornell-brg/pymtl

  Python-based hardware modeling framework

  Language:Python2354415782

• DAMO-NLP-SG/WebDesignAgent

  WebDesignAgent : Towards Effortless Website Creation

  Language:Python22931327

• alexforencich/cocotbext-axi

  AXI interface modules for Cocotb

  Language:Python209136668

• SpinalHDL/SpinalWorkshop

  Labs to learn SpinalHDL

  Language:Scala135101840

• josherich/repo-to-pdf

  repository to pdf

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• OSVVM/AXI4

  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

  Language:VHDL126111818

• jijingg/Spinal-bootcamp

  SpinalHDL-tutorial based on Jupyter Notebook

  Language:Jupyter Notebook12581546

• ucb-bar/midas

  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

  Language:Scala96332014

• Xilinx/RecoNIC

  RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

  Language:SystemVerilog9351616

• SpinalHDL/VexiiRiscv

  Like VexRiscv, but, Harder, Better, Faster, Stronger

  Language:Scala85121810

• espressif/esp32c3-direct-boot-example

  Example of ESP32-C3 (rev. 3 and later) "direct boot" feature.

  Language:CMake688918

• ProjectMitosisOS/mitosis-core

  An OS kernel module for fast **remote** fork using advanced datacenter networking (RDMA).

  Language:Rust55335

• j-marjanovic/pp-sp-reference-design

  Language:SystemVerilog386515

• Xilinx/AlveoLink

  This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multiple Alveo cards.

  Language:Verilog19404

• SpinalHDL/docker

  Language:Dockerfile4807

• bluewww/emacs-dotfiles

  My emacs dotfile, inspired by spacemacs.

  Language:Emacs Lisp3001

• joonho3020/fireaxe-firesim

  Language:Scala2300

• doofin/dependentChisel

  Chisel on Scala 3 with improved bit width inference

  Language:Scala1600

• euphgh/rootfs

  minimal rootfs configuration

  Language:Shell10