Pinned Repositories
2x2_Mesh_NoC
A 2x2 2-D Mesh NoC with Vitis HLS
4096bit-IDDMM-Verilog
4096bit Iterative digit-digit Montgomery Multiplication in Verilog
Cache
L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
ChampSim
ChampSim repository
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
corundum
Open source FPGA-based NIC and platform for in-network compute
ECC
ECC Verilog(192-bit P-field)
FFT_Convolution
64x64 convolution, the FFT Model is modified by https://www.itread01.com/content/1546333932.html
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
Spectre-RISCV
Spectre attacks(Spectre-{PHT, BTB RSB} and Spectre v4) on RISC-V ISA.
zznjupt's Repositories
zznjupt/paper-reading-list
My paper reading list and notes for various research topics
zznjupt/mirage
MIRAGE (USENIX Security 2021)