Sobel Edge Detection on Spartan 3E board usign Xilinx ISE. The input image is hardcoded and contains colour pixels despite the video output being black and white. The module displays the B&W input image and hte sobel edge detection results side by side on button presses. Input image generated through IP generation.
- Control – Datapath organization
- Area: 130 std cells, avg 14.45 cell pins (SRAM and VGA controller not included)
- Timing: 1 clock cycle per pixel
files lena_input.ngc and lena_input.mif must be copied into the project folder (xilinx ISE) for the precompiled modules to be used.