Pinned Repositories
buffer_size_est
Simple TB and equation in order to estimate buffer size required to not overfill it
cdc
CDC techniques based on Cummings pdf
Hard_Video_Processing
Hardware Video Processing on FPGA
keras-YOLOv3-model-set
end-to-end YOLOv4/v3/v2 object detection pipeline, implemented on tf.keras with different technologies
Lab_IUP_Projects
Projects that were required for the laboratory at Politechnika Gdańska 2015-2019
poker_timer
Poker Level Timer
sha256
Project done for Warsaw University of Technology's RIM course.
sierpinski_triangle
simple project for fun over christmas holidays
transistor_circuits
veriNoC
Master Thesis 2020/2022 Network on Chip
AdDraw's Repositories
AdDraw/veriNoC
Master Thesis 2020/2022 Network on Chip
AdDraw/buffer_size_est
Simple TB and equation in order to estimate buffer size required to not overfill it
AdDraw/cdc
CDC techniques based on Cummings pdf
AdDraw/Hard_Video_Processing
Hardware Video Processing on FPGA
AdDraw/keras-YOLOv3-model-set
end-to-end YOLOv4/v3/v2 object detection pipeline, implemented on tf.keras with different technologies
AdDraw/Lab_IUP_Projects
Projects that were required for the laboratory at Politechnika Gdańska 2015-2019
AdDraw/poker_timer
Poker Level Timer
AdDraw/sha256
Project done for Warsaw University of Technology's RIM course.
AdDraw/sierpinski_triangle
simple project for fun over christmas holidays
AdDraw/tinytapeout_demo
AdDraw/transistor_circuits
AdDraw/verible-linter-action
Automatic SystemVerilog linting in github actions with the help of Verible
AdDraw/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation