AdDraw/veriNoC

Issues

• Add a Verilog/SystemVerilog linting job

  #33 opened 2 years ago by AdDraw
  1

• Resource Usage analytics

  #32 opened 2 years ago by AdDraw
  0

• Flow Control Implementation

  #14 opened 4 years ago by AdDraw
  1

• Routing

  #7 opened 4 years ago by AdDraw
  1

• Backpressure systems

  #30 opened 2 years ago by AdDraw
  0

• Support for cocotb 1.6.2

  #27 opened 3 years ago by AdDraw
  0

• Methods of Arbitration

  #11 opened 4 years ago by AdDraw
  2

• Cleanup repository

  #25 opened 3 years ago by AdDraw
  0

• Create a simple `utils` python package to install through `pip`

  #26 opened 3 years ago by AdDraw
  0

• Check python formatting

  #24 opened 3 years ago by AdDraw
  0

• Faster / Better / More Stable CI

  #22 opened 3 years ago by AdDraw
  0

• Allow for easy customization of a NoC

  #21 opened 3 years ago by AdDraw
  0

• Testing

  #8 opened 3 years ago by AdDraw
  2

• Grab metrics and compile them in the spreadsheet/graph

  #6 opened 3 years ago by AdDraw
  0

• Enable Packetization of Data

  #15 opened 3 years ago by AdDraw
  2

• Advanced Synthesis

  #17 opened 3 years ago by AdDraw
  1

• Implement a Network Interface ( Terminal <-> Node connection)

  #9 opened 4 years ago by AdDraw
  0

• Add PostSynth Simulations for every NOC

  #10 opened 4 years ago by AdDraw
  1

• Topologies

  #16 opened 4 years ago by AdDraw
  0

• Create a simple mesh xy NOC

  #1 opened 4 years ago by AdDraw
  0

• CI

  #4 opened 4 years ago by AdDraw
  0

• Simple Switch -> easy configuration for 3x3, 4x4, 5x5 ports

  #5 opened 4 years ago by AdDraw
  2

• Verficate Simple Switch Formally

  #3 opened 4 years ago by AdDraw
  1

• Create a cocotb tb for the single Switch

  #2 opened 4 years ago by AdDraw
  1