/Multicycle-MIPS-in-Verilog

MIPS Multicycle CPU design in Verilog

Primary LanguageVerilogMIT LicenseMIT

MIPS processor in verilog

verilog version BSD Licence Follow me Project Initiator Repo Size

MIPS multi cycle Verilog implementation based on Computer Organization and Design

What instructions does it support?

This is an example of the instructions it supports:

add Dist, Rsrc1, Rsrc2
sub Dist, Rsrc4, Rsrc3
----------------------
not Dist, Rsrc4
----------------------
multi Rsrc1, imm
divi Rsrc1, imm
----------------------
beq Rsrc5, Src3
bne Rsrc6, Src4
----------------------
bgt Rsrc3, Src1
bge Rsrc1, Src6
----------------------
blt Rsrc4, Src2
ble Rsrc3, Src3
----------------------
j labelJump
jal labelJump and Link
----------------------
lsl Dist, Rsrc3, Shamt
lsr Dist, Rsrc5, Shamt
----------------------
and Dist, Rsrc3, Rsrc5
or Dist, Rsrc2, Rsrc4
----------------------
slt Rsrc4, Rsrc1
----------------------
sra Rsrc3, imm

Simulation


Datapath

Installation

  1. Clone the Repo
git clone https://github.com/Amir-Shamsi/Multicycle-MIPS-in-Verilog.git
  1. Run Simulate Behavioral Model for MIPS.v
  2. Enjoy the pipelined processor!